The Hyderabad Centre is bringing Academicians, Industrialists, Technologists and Scientists on one common platform in our endeavor to solve the problems confronted by the local Industry by conducting Symposia, Seminars, Conferences. IETE Hyderabad Centre conducted workshop on


 5 March, 2017

This workshop gives an overview on fundamental and abstract modeling of Verilog HDL programming for digital design circuits. These sessions deals the procedure to write a Verilog program for a hardware design, as well as test bench to simulate the design to verifying the all possible cases. This seminar talks over hardware modeling of FSM using Verilog HDL with examples. In this session, we discussed the standard programs which are useful in real time project design. Participant received handouts to popular modules in Verilog HDL. Workshop held in 2 sessions of whole 6 hours.

       Chairman addressing about IETE                     

              Welcome address by Chairman, Hyderbad Centre                                       Shri. T.Surender Reddy explaining about overview of workshop



          Modeling of digital design using Verilog HDL                        Valedictory-Prof. C R Sarma Felicitaing the Speaker